The hArtes Tool Chain

This chapter describes the different design steps needed to go from legacy code to a transformed application that can be efficiently mapped on the hArtes platform

Quantitative hardware prediction modeling for hardware/software co-design

Hardware estimation is an important factor in Hardware/Software Co-design. In this dissertation, we present the Quipu Modeling Approach, a high-level quantitative prediction model for HW/SW Partitioning using statistical methods. Our approach uses linear regression between software complexity metrics and hardware characteristics. The resulting prediction models provide essential information for such Co-design tasks, as identifying resource intensive parts of the application, helping to evaluate different mapping options, and guiding code modifications. We show that prediction models can be generated for different High Level Synthesis tools, reconfigurable devices, hardware measures, and application domains. To this purpose, we present a detailed investigation of several Quipu prediction models targeting each of these different dimensions. In addition, an extensive description is given of the targeting of the Quipu Modeling Approach to a new tool and platform within a few days. We evaluate the quality of our models by carefully investigating the error behavior, which ranges from 2.4%, for a domain-specific model targeting slices, to 39.7%, for a domain-agnostic model targeting the number of controller states. As a demonstration of the practical use of Quipu Prediction models, we present a case study of two applications. These applications were analyzed and partitioned for the Molen Machine Organization. We show how Quipu prediction models play an important role in evaluating area constraints and performing Design Space Exploration. The two applications had an increased performance of 192% and 30%.Software and Computer TechnologyElectrical Engineering, Mathematics and Computer Scienc

A Quantitative Model for Hardware/Software Partitioning

Heterogeneous System Development needs Hardware/Software Partitioning performed early on in the development process. In order to do this early on predictions of hardware resource usage and delay are necessary. In this thesis a Quantitative Model is presented that can make early predictions to support the partitioning process. The model is based on Software Complexity Metrics, which capture important aspects of functions like control intensity, data intensity, code size, etc. In order to remedy the interdependence of the software metrics a Principal Component Analysis performed. The hardware characteristics were determined by automatically generating VHDL from C using the DWARV C-to-VHDL compiler. Using the results from the principal component analysis, the quantitative model was generated using linear regression. The error of the model di?ers per hardware characteristic. We show that for ?ip-?ops the mean error for the predictions is 69%. In conclusion, our quantitative model can make fast and su?ciently accurate area predictions to support Hardware/Software Partitioning. In the future, the model can be extended by introducing extra software metrics, using more advanced modeling techniques, and using a larger collection of functions and algorithms.Computer EngineeringMicroelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc